1. Field of the Invention
The present invention relates to, e.g., a NAND flash memory, and to a semiconductor memory device and a semiconductor memory system that can store multilevel data.
2. Description of the Related Art
In a NAND flash memory, all or half of cells aligned in a row direction are connected with each of the writing or reading latch circuits through each of the bit lines. A write operation or a read operation is collectively carried out with respect to all or half of the cells (e.g., 2 to 8 kB cells) aligned in the row direction.
A write or read unit is called a page, and a plurality of pages constitute a block. Data in the memory cells are erased in units of blocks. Electrons are extracted from the memory cells by an erase operation to provide a negative threshold voltage, and introducing electrons into the memory cells by a write operation enables setting the threshold voltage to a positive value.
A multilevel memory that sets one of a plurality of threshold voltages (which will be also referred to as threshold levels hereinafter) in one memory cell to store data consisting of a plurality of bits has been recently developed. For example, data of 2 bits can be stored in one cell when 4 threshold levels are provided, and data of 3 bits can be stored in one cell when 8 threshold levels are provided. Further, data of 4 bits can be stored in one cell when 16 threshold levels are provided.
On the other hand, with the advancement of miniaturization of a device, capacitance coupling of cells adjacent to each other tends to increase. Therefore, there is a problem that a threshold level of a cell in which data has been written in the first place fluctuates with writing in an adjacent cell. To avoid this problem, there has been suggested a countermeasure that roughly writes data in an adjacent cell at a level lower than a target threshold level before finely writing the threshold level into a memory cell as a target level and then finely writes the threshold level into the memory cell as the target level, thereby suppressing a fluctuation in threshold level due to writing in the adjacent cell (see, e.g., JP-A 2007-323731 (KOKAI)).
However, data is supplied from the outside to the NAND flash memory in units of pages. Therefore, data in an adjacent cell in which data is to be subsequently written is unknown. Thus, there has been developed a technology that prepares a 2-level block in which data of n bits or smaller bits, e.g., 1 bit written at a 2-valued level is prepared separately from a multilevel block in which data of n bits as a multi-valued level into one cell, then writes data corresponding to several pages at the 2-valued level into the 2-level block initially, and moves this data to a multilevel block (see, e.g., JP-A 2007-305210 (KOKAI)).
However, for example, when storing 4 bits in 1 cell, or when writing 3 bits in 1 cell, a writing speed is lower than that in 2-level writing. Therefore, an increase in writing in the 2-level block is not large. However, when writing 2 bits (4 levels) in 1 cell, a time required to write data in the 2-level block is not greatly different from a time required to write data in a four-level block. Therefore, an increase in writing in the 2-level block is relatively large, thereby resulting in a problem that writing performance is degraded.
Accordingly, a semiconductor memory device that can suppress an influence of capacity coupling of cells adjacent to each other and write data at a high speed has been demanded.